Altera up2 manual

Altera Corporation University Program UP2 Education Kit User Guide Note (1) P2 Inside Outside Page 8 University Program UP2 Education Kit User Guide D1 through D16 LEDs The UP2 Education Board contains 16 LEDs that are pulled-up with a Ω resistor. An LED is illuminated when a logic 0 is applied to the female header associated with the LED. The UP Squared Series is powered by Intel® Atom™ x5-E and clocks up to GHz with only 4W SDP and W TDP. Inheriting the pin GP-bus from the first generation of UP, although this time controlled by Altera FPGA MAX 10, UP² (UP Squared) comes with a range of additional features. Makers will enjoy up to 8GB of RAM, up to GB. When compiling a design for downloading to an Altera UP2 Board, select the appropriate device for each piece of code that is compiled. With the source file as the current file, select Assignments | Device. For the MAX chip on the left of the board, the device family is MAXS.

Term Project Overview Yong Wang Introduction Goal familiarize with the design and implementation of a simple pipelined RISC processor What to do Build a processor from scratch (single-cycle implementation) Add some functions Pipeline datapath, pipeline control, hazard detection unit, forwarding unit, branch hazard handling unit Write an assembler that detects data hazard and optimizes the code. Manual: Tektronix Oscilloscope manual (KB) Oscilloscope Tutorial; Other: Altera UP2 UP-1 board info; PALASM source files. (PALASM is a simple HDL.) Altera's UP-3 info; Make mif files (mif = memeory initialization file) for Quartus with this executable file (with thanks to Adam Barnett). When compiling a design for downloading to an Altera UP2 Board, select the appropriate device for each piece of code that is compiled. With the source file as the current file, select Assignments | Device. For the MAX chip on the left of the board, the device family is MAXS.

University Program UP2 Education Kit User Guide ® Altera, MAX II, MAX S, Quartus II, EPMS, FLEX, FLEX 10K, EPF10K20, EPF10K70, ByteBlaster II, EPC1, and AHDL are trademarks and/or service marks of Altera Corporation in the United States and other Innovation Drive countries. Manual, the Control Panel utility, reference designs and demonstrations, device datasheets, tutorials, and a set of laboratory exercises • CD-ROMs containing Altera’s Quartus® II Web Edition and the Nios ® II Embedded Design Suit Evaluation Edition software. • Bag of six rubber (silicon) covers for the DE2 board stands. The UP Squared Series is powered by Intel® Atom™ x5-E and clocks up to GHz with only 4W SDP and W TDP. Inheriting the pin GP-bus from the first generation of UP, although this time controlled by Altera FPGA MAX 10, UP² (UP Squared) comes with a range of additional features. Makers will enjoy up to 8GB of RAM, up to GB.